PCI Express® AMBA™ AXI®/AHB® Bridge
ARM CPUs have become the de facto choice for computing in the embedded world including consumer electronics ranging from mobile and handheld devices to computer peripherals like hard drives and routers. In order to meet the increasing demand of ARM-based SoCs starving for highest throughput, lowest power consumption and lowest latency, Snowbush IP has architected a sophisticated bridge solution to connect either of the two high performance ARM CPU-based buses - AMBA AXI and AMBA AHB to PCI Express. The bridge encompasses all system level complexities like DMA, mailbox, interrupt, MSI and power management.
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FeaturesBlock DiagramDeliverablesProducts
- Synthesizable Verilog RTL
- Sample Testbench for Simulation
- Sample Synthesis Scripts
- Sample Static Timing Analysis
- User Manual and Application Note
Feature Highlights
- Low Latency and High Throughput Architecture
- Supports PCI Express® Base Specification 1.1 and 2.0
- Choice of either Root Mode or Endpoint Mode for PCI Express® at Power-up
- Supports MSI or Legacy Interrupt for PCI Express
- Supports system interrupt for ARM or Internal processor
- Supports EEPROM controller to load boot data through SPI interface
- Support Mailbox between PCI Express® and AMBA AHB or AMBA AXI Bus
- Supports Error Handling of both PCIe and AHB or AXI Protocols
Power Management
- Supports all required and optional PCI Express® power management states: L0, L0s, L1, L2 & L3
- ClkReq mechanism for low power mode in mobile form factors
- Supports Beacon and Wake-Up mechanism on PCIe Link
High Throughput
- High throughput with support for 4 outstanding AXI to PCIe memory read transactions
- Supports wrap cycles on the AMBA AHB bus
- Supports 1st Party DMA with ability to accept DMA Memory WR/RD commands from PCIe and AMBA Master
- Handles out-of-order read-completions from PCIe targets
- Multiple descriptors per DMA channel
- Local CPU Off-load Support through Concurrent DMA Write and Read
Flexible Addressing/Datawidth
- Supports both 32b/64b addressing from PCIe to AXI or AHB bus
- Configurable AMBA Databus - Master and Slave independently configurable to either 32-bit or 64-bit
- User selectable 5 variable windows from AMBA to PCIe address translations
- User selectable 4 variable windows from PCIe to AMBA address translations
- Up to 4 Base Address Registers (BARs) available in root mode address translation
Interrupt/Mailbox
- Interrupt generation from local CPU to external CPU
- Interrupt generation from external CPU to internal CPU
- Mailbox interrupt registers from internal CPU to external CPU
- Mailbox interrupt registers from external CPU to internal CPU
Bridge Registers
- Dedicated Bridge internal registers in PCIe clock domain for software accessibility during internal power save
- Bridge internal registers accessible from both PCIe and AMBA bus
| Part No |
Description |
Foundry |
Geometry |
| SBSUBAXIPCIEX | Integrated Solution - AMBA AXI Bridge for PCI Express Gen1/Gen2 x1/x4 Controllers | N/A
| N/A
|
| SBSUBAHBPCIEX | AMBA AHB Bridge for PCI Express Gen1/Gen2 x1/x4 Controllers | N/A
| N/A
|
| SBSUBMPASDDR2 | Integrated Solution - Multi-Port Intelligent Arbiter and Scheduler (MPAS) with Optional AHB or AXI Interface with DDR 2 Controller | N/A
| N/A
|
| SBSUBMPASDDR3 | Integrated Solution - Multi-Port Intelligent Arbiter and Scheduler (MPAS) with Optional AHB or AXI Interface with DDR 2 Controller | N/A
| N/A
|
| SBSUBPCIE2SAT | Integrated Solution - PCI Express to AHCI-compliant SATA Host Controller | N/A
| N/A
|
| SBSUBPCIE2DDR | Integrated Solution - PCI Express to DDR Controller | N/A
| N/A
|
 SBSWEMPCIE9P | PCI Express Gen1/Gen2 Switch up to 9 Ports with Optional Embedded Endpoint | N/A
| N/A
|
