Years of designing Multi-Standard SerDes that meet a wide range of data rates and the most demanding performance specifications have allowed Snowbush IP to develop world-class stand-alone phase-locked loop (PLL) IP. Snowbush PLLs are designed in standard digital CMOS technologies and can be used for SoC clock generator applications. Using Snowbush's proprietary fractional synthesis technology, the PLL IP is capable of supporting reference clock frequencies that are non-integer multiples of the output high-speed clock.

The PLL IP also feature automatic digital calibration used to adjust critical parameters of the PLL to ensure reliable operation over process, voltage, and temperature variations. Various low-power states are available to enable ultra low-power operation. A wide range of testability features are also built-in to the IP, including diagnostic digital test bus and devoted analog test pad for coverage during production testing.

Snowbush also offers Line-Lock PLL (LLPLL) IP, custom designed for RGB graphics and/or video applications. The LLPLL supports a wide range of graphics display formats from VGA (640 x 480 resolution) up to UXGA (1600 x 1200 resolution).