Snowbush IP 10G PHYs are based on a proprietary hybrid analog/digital architecture that offers low power and compact area, while exceeding key electrical specifications, like transmit jitter and receive jitter tolerance, for robust performance in challenging SoC environments. Advanced Decision Feeback Equalization (DFE) is employed together with Continuous Time Linear Equalization (CTLE) to provide excellent jitter tolerance even with long, legacy backplanes.

As the leader in high-performance, high-speed serial interface IP, Snowbush IP is the first company to offer advance 10 Gb/s serial IP designs in 65nm and 40nm, with working silicon and characterization reports available today.

Snowbush IP 10G PHYs include several important features and advantages designed to ensure the successful integration of these high performance I/Os into your ASIC products. Features like on-chip eye plotting capability to allow end users the ability to see the quality of the equalized eye and evaluate system margin in real time, without the need for external scopes. The 10G PHYs also features highly scalable power consumption, and sophisticated power management modes for ultra low-power operation. Robust Manufacturing test support is provided via BIST, 7 internal loop-back modes, and on-chip pattern generators and checkers supporting both user-defined and industry-standard PRBS data patterns.