Snowbush IP 10G PHYs are designed for easy integration into SoC designs in 65nm and 40nm processes, with a roadmap to 28nm. The PHYs are compliant with a number of 10G-related standards, such as XFI, 10GBase-KR, CEI-11G, and 10G Fibre Channel, and cover data rates from 1Gb/s up to as high as 12.5Gb/s, enabling today's Networking and high-speed backplane solutions as well as future advanced storage solutions, such as SAS 12G.
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Snowbush IP 10G PHYs are based on a proprietary hybrid analog/digital architecture that offers low power and compact area, while exceeding key electrical specifications, like transmit jitter and receive jitter tolerance, for robust performance in challenging SoC environments. Advanced Decision Feeback Equalization (DFE) is employed together with Continuous Time Linear Equalization (CTLE) to provide excellent jitter tolerance even with long, legacy backplanes.
As the leader in high-performance, high-speed serial interface IP, Snowbush IP is the first company to offer advance 10 Gb/s serial IP designs in 65nm and 40nm, with working silicon and characterization reports available today.
Snowbush IP 10G PHYs include several important features and advantages designed to ensure the successful integration of these high performance I/Os into your ASIC products. Features like on-chip eye plotting capability to allow end users the ability to see the quality of the equalized eye and evaluate system margin in real time, without the need for external scopes. The 10G PHYs also features highly scalable power consumption, and sophisticated power management modes for ultra low-power operation. Robust Manufacturing test support is provided via BIST, 7 internal loop-back modes, and on-chip pattern generators and checkers supporting both user-defined and industry-standard PRBS data patterns.
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- Specification and Integration Manual
- GDSII and Layer Map Files
- Library Exchange Format (LEF) defining size and pin locations
- Verilog PHY Behavioral Model and Testbenches
- Timing Constraint File
- DRC and LVS reports
- Netlist in SPICE format for LVS
- Supports data rates from 1Gb/s to 12.5Gb/s
- Supports single or multi-lane configurations
- Leverages automatic digital calibration to ensure reliability and maximize yields
- Excellent jitter performance due to extensive use of on-chip regulation
- CMU technology includes fractional synthesis to support spread-spectrum clocking and non-integer reference clock frequencies
- Extensive testability features including various loopback modes, on-chip pattern generator and checker, and on-chip eye plotting capability
- Highly programmable Transmitter and Receiver allowing excellent system performance while minimizing power consumption
- Programmable driver swing, transmit pre-emphasis, and output driver slew rate
- Programmable linear receiver equalization, and DFE for channel equalization
- Supports various power savings modes for ultra low-power operation, including IDDQ
- Internal Power Supplies 1.0/1.1/1.2V from core
- External Power Supplies 1.8/2.5 and 0.9/1.0
| SBSER4000T65G||1-10Gb/s Multi-Standard SerDes||TSMC||65nm|