PCI Express® Controllers
The Snowbush PCI Express Controllers have been architected to achieve very low latency and power with low gate-count. They achieve the industry's highest throughput and support advanced power management features. Their unique design ensures customers can achieve quick timing closure, and a very small silicon footprint. The controllers include a practical and streamlined user interface that simplifies the integration of the cores with the customer's logic.
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FeaturesBlock DiagramDeliverablesProducts
- Synthesizable Verilog RTL
- Testbench and Models for Simulation
- Sample Synthesis Scripts
- Sample Static Timing Analysis
- User Manual for Integration and Application Notes
PCI Express® Spec Supported
- PCI Express Specification 2.0 (Gen 2)
- PCI Express Specification 1.1 (Gen 1)
- PIPE Specification 2.0
Design for Testability/Design for Debugability
- Streamlined User Interface with clear functional signal subgroups
- Controllability for critical device parameters
- Debug bus to capture critical state machines and internal signals
Parameterized core
- Highly Parameterized RTL for easy configuration depending on your custom requirements
- Supports both Cut-Through and Store-and-Forward schemes for forwarding transmitted packets
- Core operates at allowed speeds across all lane configurations
- User configurable Virtual Channels and Traffic Class mapping
- Selectable ECRC and Advanced Error Reporting Support
- Configurable Type-0 (Endpoint) or Type-1 (Root Port, Switch Port) Config Headers
High Performance
- Supports up to 8 Virtual Channels and 8 Traffic Classes
- High Performance with Low Latency, Maximum throughput, Multiple Pipelined Memory WR/RD capability
- Highly Configurable Retry buffer design for low latency and area depending on user application
- Non-Blocking Architecture with Maximum PCI Express® Link Utilization
- Multifunction Endpoints
- Small Silicon Footprint - Suitable for Multiple Instances of the Core in Single ASIC/FPGA
- Supports operation with 8-bit, 16-bit, and 32-bit PIPE interface
Reliability
- Silicon Validated Design
- Designed for testability and debugability
- Multiple entries in the PCI-SIG PCI Express Integrators List
- Thoroughly verified against industry leading PCI Express verification suites
- Extensive list of Interoperable PCI Express vendors
Feature Highlights
- Supports PCI Express Specification 2.0 (Gen2), and 1.1 (Gen1)
- Supports PIPE Specification 2.0
- Supports Endpoint, Root Port, Dual (Root/Endpoint) and Switch Port
- Supports multiple lane configuration - x1, x4
- Snowbush IP's PCI Express® IP Cores are silicon-validated, highly configurable, and scalable - ready to meet custom design requirements.
- High Performance with Low Latency, Maximum throughput, Multiple Pipelined Memory WR/RD capability
- Supports up to 8 Virtual Channels and 8 Traffic Classes
- Non-Blocking Architecture with Maximum PCI Express® Link Utilization
- Streamlined User Interface with clear functional signal subgroups
- Small Silicon Footprint - Suitable for Multiple Instances of the Core in Single ASIC/FPGA
- Highly Parameterized Core supporting both cut-through and store-and-forward schemes
- Supports operation with 8-bit, 16-bit, and 32-bit PIPE interface
- Configurable Retry buffering scheme for low footprint and latency
- Supports Comprehensive PM support with L0,L0s,L1,L2, L3, and CLKREQ
- Supports Beacon and Wake-Up mechanisms
- Controllability for critical device parameters
- Debug bus to capture critical state machines and internal signal
- Supports multiple functions
- Supports PCI Express® Advanced Error Reporting
- Multiple entries in the PCI-SIG PCI Express Integrators List
- Thoroughly verified against industry leading PCI Express verification suites
Power Management Features
- Supports all required and optional PCI Express Power Management features
- Supports Beacon and Wake-Up mechanisms
- Supports all PM states L0, L0s, L1, L2 & L3
- ClkREQ mechanism for low power mode in mobile form factors