DDR memory interfaces have grown more complex in today's SoCs. Today's technology requires the interface to be capable of handling the demands for reading and writing data to and from DDR memories across multiple internal agents vying for the same DDR resource. Snowbush IP has responded to these challenges by developing a carefully architected design for our DDR 1, 2, and 3 Controllers that delivers controlled bandwidth, the lowest latency, and exceptionally low gate count. The DDR controller core handles all complex functional aspects of controlling DDR SDRAM which includes initializing the memory devices, translating the read and write requests from the application interface into the standard SDRAM command signals, and performing ECC for the memory banks.

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