Multi-Standard SerDes

Our serializer-deserializer (SerDes) macros provide all key physical layer functions for creating full-duplex, multi-gigabit serial interfaces for a broad range of serial I/O standards. And, like all Snowbush IP cores, our multi-standard SerDes are backed by a unique commitment to design support for integration, customization and development of complementary circuit blocks.

Snowbush SerDes offer several important features and advantages designed to ensure the successful integration of high-speed serial I/O into your ASIC products:

• Superb transmit jitter, receive jitter tolerance and noise immunity to ensure robust SoC performance.
• A complete set of test features including multiple data loop-back modes, recovered clock loop-back modes, data pattern generator/checker, analog test bus and mux.
• The utilization of proprietary hybrid analog/digital architecture in several versions to optimize performance, power and silicon area.
• Programmable receive equalization in several versions.
• Extensive use of digital calibration where practically every important analog parameter is adjusted, most automatically at startup, results in fast error-free porting to multiple technologies.
• Includes fractional-n synthesis, allowing for non-integer reference frequencies and frequency-spreading.

For more details, including availability, custom solutions and PCI Express® Gen 2 applications, please contact sales.